Simulation of FPGA based Buffered Security Enabled Encoders

This book deals with the simulation of various Encoders through FPGA based system to add security in embedded systems. A buffered based implementation has been proposed which accept a stream of data form input port; store the data into the buffer. The encryption technique operates on the data to generate the intermediate encrypted data stream through simulated hardware. Triangular Encoder deals with string / block as input and produces the string / block as output based on the XOR operation. The XOR operation is done on a fixed size data block, which is taken from the buffer storage. The number of iterations depends on the size of the block of data bits in the data stream. This encoder follows the principle of block cipher technique and symmetric in nature, hence decoding is done following the same procedure. The buffer can store the encrypted data also. This simulation gives the hardware definition/ RTL for buffer based encryption.

Autorentext

Ms. Mousumi Saha was born in 1981. She is an Information Technology Engineer and has obtained her M.Tech degree in computer Science with VLSI specialization in 2008. Presently she is working with Sikkim Manipal University as an assistant professor. Mrs. Mousumi's research interest includes VLSI, computer networks and security.