Source Level Debugging of Verilog Designs

Debugging is a very crucial part of hardware design cycle. Once a design is completed, all the possible faults need to be located and corrected. Although the complexity of hardware design is ever increasing, debugging is still mostly performed manually. Today, debugging has become a very painstaking and time consuming task. Model-based diagnosis provides a solid foundation for automated debugging and fault localization but sometimes the quality of the results is questionable as too many diagnosis candidates are reported. The work presented in this book shows how to apply model-based diagnosis to debugging of synthesizable Verilog designs. Moreover, Two extensions of the model based debugging theory to improve the debugging process in terms of reduction in the number of diagnosis candidates reported, are proposed.

Autorentext

Naveed Riaz received a Ph.D. from Graz University of Technology (2008) in Software Engineering, a M.S. in Software Engineering (2005) from National University of Sciences and Technology (NUST), Rawalpindi, Pakistan and a M.Sc. degree in Computer Science (2001) from Bahria Institute of Management and Computer Sciences, Islamabad, Pakistan .