Source-Synchronous Networks-On-Chip

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. It provides circuit-level details of the NoC and includes architectural simulations of the NoC.

Describes novel methods for high-speed network-on-chip (NoC) design Enables readers to understand NoC design from both circuit and architectural levels Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art Includes supplementary material: sn.pub/extras

Inhalt
Introduction.- Clock Distribution for fast Networks-on-Chip.- Fast Network-on-Chip Design.- Fast On-Chip Data transfer using Sinusoid Signals.- Conclusion and Future Work.