SRAM Architectures

CMOS digital ICs are enabling the technology for the modern information age. Digital systems handle large amounts of information at high speeds. Such products demand low-priced memories with low-power consumption, high-speed operation, high density, and small package size. The architecture of the memory structure has a considerable impact on the performance of the system. Over the years, technology advances have been driven by memory designs of higher and higher density. While designing SOC, system architects need to resolve a number of complex issues in high-performance system applications. However, one of the fundamental problems in these applications is Memories - the bottlenecks and challenges of system performance often reside in its memory architecture. Memory developers have to design memories to address the issues in bandwidth, latency, density, power and cost. Unfortunately, it is not possible for a single memory technology to address all these issues with distinct advantages. In this book an attempt is made to investigate various SRAM architectures for different applications and study of Deep Submicron Effects affecting functionality and design topology for SRAMs.

Autorentext

Anuj Gupta obtained his Master of Science in "VLSI System Design" with Distinction from Coventry University, UK in 2009. He is an Associate Member of IETE, India since 2007. He is currently a Senior Design Engineer in Memory Solution Group at GlobalFoundires, NY. In his experience of a decade, Anuj has worked on various full custom layout projects.