System Level ESD Protection

An invaluable reference tool for anyone attempting to integrate systems-on-chip and on-package with system-level ESD protection, this handbook addresses key aspects of analog integrated circuits and systems design, including co-design methodology.

This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection. It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.

Provides a systematic approach to on-chip ESD protection for system-level IC pins Describes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structure Includes a comprehensive description of wafer- level and component-level test methodologies Includes supplementary material: sn.pub/extras

Autorentext

Dr. Vladislav Vashchenko is Director of ESD group at Maxim Integrated Corp responsible for major ESD development aspects across the entire $2.4B enterprise. During previous decade he was leading the ESD group at National Semiconductor Corp. and the decade till then he was a key contributor in reliability department of SRI Pulsar(Moscow). He received MS, Engineer-Physicist and Ph.D. in Physics of Semiconductors from Moscow Institute of Physics and Technology (1990) and Doctor of Science in Microelectronics degree (1997). He is author of over 140 U.S. patents and over 100 papers in the field, co-author of books Physical Limitation of Semiconductor Devices (2008) and ESD Design for Analog Circuits (2010,).

Mirko Scholz received the degree Diplomingenieur (FH)" from the University of Applied Sciences in Zwickau (Germany) in 2005 and the PhD degree in Electrical Engineering from the Vrije Universiteit in Brussels (VUB) in 2013. In April 2005 he joined the imec ESD team as ESD researcher where he authored and coauthored more than 70 publications, tutorials and patents in the field of ESD reliability and ESD testing. Since 2007, he has been a member of the Device Testing Working Groups of the ESDA standards committee where he currently chairs working group 5.6 (Human Metal Model).

Inhalt

System 1 Level ESD design.- System Level Test Methods.- On-Chip System Level ESD Devices and Clamps.- Latch-up at System-Level Stress.- IC and Systemn ESD Co-Design.