SystemVerilog Assertions and Functional Coverage

This book offers a hands-on, application-oriented guide to the language and methodology of SystemVerilog Assertions and SystemVerilog Functional Coverage. Includes easy-to-understand examples, simulation logs and applications derived from real-world projects.

Covers both SystemVerilog Assertions and Sytem Verilog Functional Coverage language and methodologies Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book Includes supplementary material: sn.pub/extras

Autorentext

Ashok Mehta is a senior manager in TSMC's CPU/SoC Architecture and Methodology group working on System and 3DIC design projects. In the past, Ashok worked in engineering and management positions at DEC, Data General, Intel and AMCC. He has extensive experience in Design/Verification of complex SoC and Processor devices. He holds nine US patents on ESL and 3DIC designs. Ashok holds a MSEE from University of Missouri.

Inhalt
Introduction.- System Verilog Assertions.- Immediate Assertions.- Concurrent Assertions Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell.- Operators.- System Functions and Tasks.- Multiple clocks.- Local Variables.- Recursive property.- Detecting and using endpoint of a sequence.- 'expect'.- 'assume' and formal (static functional) verification.- Other important topics.- Asynchronous Assertions !!!.- IEEE-18002009 Features.- SystemVerilog Assertions LABs.- System Verilog Assertions LAB Answers.- Functional Coverage.- Performance Implications of coverage methodology.- Coverage Options (Reference material).