SystemVerilog Assertions and Functional Coverage

This book offers a hands-on, application-oriented guide to the language and methodology of SystemVerilog Assertions and SystemVerilog Functional Coverage. Includes easy-to-understand examples, simulation logs and applications derived from real-world projects.

in its entirety the latest IEEE-1800 2012 LRM syntax and semantics both SystemVerilog Assertions and SystemVerilog Functional Coverage language and methodologies Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies Explains each concept in a step-by-step fashion and applies it to a practical real life example Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book Includes supplementary material: sn.pub/extras

Autorentext
Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working first as a CPU design engineer, moving on to hardware design verification of the VAX11-785 CPU design. He then worked at Data General, Intel (first Pentium design team) and after a route of a couple of startups, worked at Applied Micro and TSMC. He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs and at TSMC he released two industry standard Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL. Lately, he has been involved with 3DIC design verification challenges at TSMC which is where SystemVerilog Assertions played an instrumental role in stacked die SoC design verification. Ashok earned an MSEE from University of Missouri. He holds 13 U.S. Patents in the field of SoC and 3DIC design verification.

Inhalt
Introduction.- System Verilog Assertions.- Immediate Assertions.- Concurrent Assertions Basics (sequence, property, assert).- Sampled Value Functions $rose, $fell.- Operators.- System Functions and Tasks.- Multiple clocks.- Local Variables.- Recursive property.- Detecting and using endpoint of a sequence.- 'expect'.- 'assume' and formal (static functional) verification.- Other important topics.- Asynchronous Assertions !!!.- IEEE-18002009 Features.- SystemVerilog Assertions LABs.- System Verilog Assertions LAB Answers.- Functional Coverage.- Performance Implications of coverage methodology.- Coverage Options.