Test and Reliability of SRAM Memories

This book considers the following problems in the domain of test and reliability of SRAM memories: optimizing test flow using stress conditions; statistical simulation for very low probabilities; variability analysis of an SRAM test-chip; fault tolerance in random addressed memories. Although the problems considered are all related to SRAM, some solutions found may also be applied in other domains. The Monte-carlo based simulation method described here is a general purpose method. The fault tolerance technique proposed can be used in different kind of memories, and its mathematical formulation can also be applied in other domains like logic synthesis for example. The methodology proposed to optimally set stress conditions during SRAM test can be adapted to any kind of circuit. The author covers SRAM problems and proposes innovative solutions that can be applied or adapted to different contexts.

Autorentext

Renan A. Fonseca has a BS degree in Computer Engineering from UFRGS (Brazil) and a BS degree in Telecommunication Engineering from INPG (France). He received his PhD degree in 2011 from Montpellier University(France). The topic of his doctoral research was Test and Reliability of SRAM Memories.