Test Generation of Crosstalk Delay Faults in VLSI Circuits

Is intended for design engineers and researchers in the field of VLSI and embedded system design Introduces readers to deterministic and simulation-based algorithms for testing crosstalk delay faults in VLSI circuits Provides a review of various test generation algorithms for crosstalk delay faults

Autorentext
Dr. S. Jayanthy is a Professor at the Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore, India. She received her Master's and PhD from PSG College of Technology and Anna University, Chennai respectively. Prof. Jayanthy's research interests are in VLSI Design & Testing, Genetic Algorithms and Embedded Systems. With more than 20 years of teaching experience, she has published 2 chapters and more than 40 research papers in journals and for national and international conferences and has organized a number of workshops and national conferences in the areas of VLSI, Embedded systems and IOT. She is a life member of Indian Society for Technical Education and Institution of Electronics and Telecommunication Engineers
Dr. M.C. Bhuvaneswari is an Associate Professor at the Department of Electrical and Electronics Engineering, PSG College of Technology, Coimbatore, India. She received her BE in Electronics and Communications Engineering from Madras University, and her ME and PhD from Bharathiar University. Her research interests include Applied Electronics, VLSI Design and Testing, Genetic Algorithms, Digital System Design, and Microprocessors. She has published a book on VLSI and Embedded systems (2015) and authored more than 90 research papers in journals and for national and international conferences. She is a life member of Indian Society for Technical Education, Institute of Engineers (India), Computer Society of India and Systems Society of India. Prof Bhuvaneswari was honored with Dakshinamoorthy award instituted by PSG College of Technology for Teaching Excellence in the year 2010

Inhalt
Chapter 1. Background and Review of Crosstalk Delay Fault Models and the Crosstalk Effects.- Chapter 2. Review of Test Generation Techniques for Crosstalk Delay Faults.- Chapter 3. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Modified PODEM and FAN Algorithm.- Chapter 4. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults using Single-Objective Genetic Algorithm.- Chapter 5. An Automatic Test Pattern Generation Method for Crosstalk Delay Faults Using Single-Objective Particle Swarm Optimization.- Chapter 6. Simulation of Asynchronous Sequential Circuits using Fuzzy Delay Model.- Chapter 7. Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential Circuits. <p