Test Infrastructure Design

Current-generation SOCs contain a heterogeneous mix of embedded cores, which include not only flat (non-hierarchical) digital modules, but also analog and hierarchical modules. The increase in SOC complexity has also been accompanied by the development of more versatile automatic test equipment (ATE). This book presents methods for modular test of heterogeneous SOCs, whereby test cost is reduced by combining effective test infrastructure design with efficient utilization of ATE resources. Test infrastructure design refers to the design and optimization of test wrappers and test access mechanisms, as well as test scheduling for efficient resource utilization.

Autorentext

Anuja (Sehgal) Banerjee received her PhD degree from Duke University, and her B.E. degree from University of Mumbai. She is the recipient of best paper awards at IEEE ICCD 2005, and IEEE ITC 2008. She has two US patents. Krishnendu Chakrabarty is Professor of Electrical and Computer Engineering at Duke University, USA (www.ee.duke.edu/~krish)