Test Vector Reordering Method for Low Power Testing

The book investigates test vector reordering algorithm for minimizing the power dissipation during testing of VLSI circuits. Testing plays a key role in design flow and is the major challenging task for design and test engineers. Power dissipation is critical problem during testing phase. The test vectors generated from Automatic Test Pattern Generator used for testing are statistically independent which leads to more power dissipation. The testing power can be reduced by reordering the sequence of test vectors. The reordering algorithm is developed using the graph theory with heuristic concept to find more sub-optimal solutions. Five functional metrics such as Cosine, Hamming, Mahalanobis, Minkowski and Seuclidean are considered for reordering the test vectors. Don't care replacement method is also proposed for reordered test set to reduce further the transitions in the CUT. Both the methods are implemented and simulated in ISCAS85 benchmark circuits to evaluate the transitions and average power. The results show that transitions and average power are reduced considerably for functions other than hamming distance when compared with unordered test set and existing methods.

Autorentext

Dr.K.Paramasivam got UG & PG engineering degree in 1995 & 97 from Bharathiar University. He got PhD(Low power VLSI Testing) at Anna University Chennai in 2009. Presently he is with Bannari Amman Institute of Technology, TN, India. He has 16 & 10 years of teaching and research experience. His publications are 17 journals & 41 Conf. proceedings.