The VAMP Memory Unit

This work is devoted to the formal verification of
the VAMP memory unit (MU) and based on the work
carried out in [Dal06]. The new design of the MU,
developed here, contains translation look-aside
buffers (TLB) for fast virtual address translation
inside the memory management units (MMU) and supports
accesses to external devices.
A computer-aided verification tool used throughout
the whole work is an interactive theorem prover
Isabelle/HOL bound [Tve05] with the NuSMV [CCG+02]
and SMV [McM99] model checkers. The results
(correctness proofs and models of hardware blocks)
are presented as Isabelle mathematical theories. The
work is described formally and paper-and-pencil
proofs are provided.

Autorentext

Born in 1979. He received the MSc and PhD degrees in computer science from Saarland University (Germany), in 2002 and 2006, respectively. From 2006 to 2008, he was a director of Institute for Computer Science in Pacific National University (Russia). Now, he is deputy vice-president for science of Saint-Petersburg State University of Civil Aviation.

Klappentext

This work is devoted to the formal verification ofthe VAMP memory unit (MU) and based on the workcarried out in [Dal06]. The new design of the MU,developed here, contains translation look-asidebuffers (TLB) for fast virtual address translationinside the memory management units (MMU) and supportsaccesses to external devices.A computer-aided verification tool used throughoutthe whole work is an interactive theorem proverIsabelle/HOL bound [Tve05] with the NuSMV [CCG+02]and SMV [McM99] model checkers. The results(correctness proofs and models of hardware blocks)are presented as Isabelle mathematical theories. Thework is described formally and paper-and-pencilproofs are provided.