Time-to-Digital Converter dedicated to Dividerless ADPLL applications

The book presents a novel Time-to-Digital Converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a Gated Ring Oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. Contents: 1) An Enhanced Variable Phase Accumulator with Minimal Hardware Complexity Dedicated to ADPLL Applications. 2) A 15b, Sub-10ps resolution, Gateable Pseudo-Delay Ring Oscillator Time-to-Digital Converter for wide range RF Applications. 3) A new hybrid TDC based on GRO-Pseudo Delay architecture with fractional code and wide time range detection for divider-less ADPLL. Complete list of Authors: Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi and Kamel Besbes.

Autorentext

Sehmi Saad nasceu em Versailles, França, em 1985. Recebeu o doutoramento em engenharia microelectrónica (ciências físicas) pela Universidade de Monastir, Tunísia, em 2017. Os seus interesses de investigação incluem circuitos integrados RF mistos/analógicos em tecnologia CMOS, com particular ênfase na concepção de sintetizadores de frequência AD-PLL de banda larga.