Transactors in SystemC

System-on-chip (SoC) is a major revolution taking place in the design of integrated circuits due to the unprecedented levels of integration possible. To specify, design, and implement complex SoC systems, the need arises to move beyond existing register transfer level (RTL) of abstraction. A new modeling method, transaction level modeling (TLM) has been proposed recently to fulfill this need. TLM modules communicate with each other through function calls and allow the designers to focus on the functionality, while abstracting away implementation details. At the RTL,however, different modules communicate through pin level signaling. SoC design methodologies involve the integration of different intellectual property (IP) blocks modeled at different levels of abstraction. Therefore a special module or channel is needed in order to link modules, IPs, designed at different levels of abstraction. This module, called transactor can be modeled using a finite state machine (FSM) providing a functional specification of the protocol's behavior. In this book, several approaches of specifying transactors and their automatic generation have been discussed.

Autorentext

Tareq Hasan Khan is now doing Ph.D. in the department of Electrical and Computer Engineering of the University of Saskatchewan in Canada on Biomedical Imaging. He got his M.A.Sc. from Concordia University in Canada in 2007. His research interest includes embedded systems and biomedical imaging.