Transistor-Level Defect-Tolerant Techniques for Reliable Design

In this book, detailed investigation of a recently proposed transistor-level defect-tolerant technique for nanoelectronics is performed. The investigated technique replaces each transistor by an N^2-transistor structure (N=2,3 ,k) and guarantees defect tolerance of all permanent defects of multiplicity (N-1) in each transistor structure. The theoretical and experimental analysis for the defect tolerance of stuck-open and stuck-short defects for quadded transistor structure i.e.,(N=2) is extended for the nona transistor structure i.e.,(N=3). Comparison of defect tolerance of transistor structures (N=2,3) against other techniques like Triple Intervowen Redundancy (TIR) and Quadded Logic (QL) is carried out experimentally. It is shown that the combinations of defect tolerance at both the transistor level and gate level have significantly improved circuit defect tolerance. For this, combination of Triple Modular Redundancy (TMR) with majority gate implemented with N^2-transistor structure is investigated in this thesis. Application of N^2-transistor structure for handling soft errors is also investigated and a novel approach based on quadded transistor structure is proposed.

Autorentext

I completed B.E. and M.E.(Computer Systems Engg.) from N.E.D. University of Engg. & Tech., Pakistan in February 2003 and June 2006 respectively. After that, I completed M.S.(Computer Engg.) from K.F.U.P.M. in June 2009. I joined H.B.C.C as Lecturer in CSET Unit in October 2009. My areas of interest are Digital System Design and Computer Networking.