Ultra-Low Energy Domain-Specific Instruction-Set Processors

General overview and context

Global state-of-the-art overview

Energy consumption breakdown for embedded platform targets

High level embedded arch and compiler requirements

Overall architecture exploration framework

Clustered loop buffer and data cluster organisation

Multi-threading in uni-threaded processors

Indirectly addressed arrays and dynamic data structure handling on scratchpad memories

Asymmetric foreground memory organisation

Exploiting word-width information in the processor datapath

Advanced strength reduction in shift-add based operations

Bioimaging application demonstrator

A systematic methodology for exploiting word-width information in embedded compilers Software method to enable heterogeneous data parallelism (SIMD) Technique for a context-driven strength reduction for constant multiplications, including a trade-off with application accuracy requirements Includes supplementary material: sn.pub/extras

Inhalt
Global State-of-the-Art Overview.- Energy Consumption Breakdown and Requirements for an Embedded Platform.- Overall Framework for Exploration.- Clustered L0 (Loop) Buffer Organization and Combination with Data Clusters.- Multi-threading in Uni-threaded Processor.- Handling Irregular Indexed Arrays and Dynamically Accessed Data on Scratchpad Memory Organisations.- An Asymmetrical Register File: The VWR.- Exploiting Word-Width Information During Mapping.- Strength Reduction of Multipliers.- Bioimaging ASIP benchmark study.- Conclusions.