Ultra Low Phase Noise PLL Frequency Synthesizer for Ku Band

Satellites are crucial in global communications, necessitating widespread transceiver use. Frequency bands, carefully chosen to prevent interference, employ Phase-Locked Loops (PLLs) as synthesizers. Designing a single-chip PLL for efficient frequency multiplication is vital in today's tech landscape. Literature reveals a gap in research for the Ku band (12-18 GHz), lacking single-chip, wideband PLLs. This work introduces a 12-18 GHz charge pump-based integer-N PLL, compact at 0.076mm², designed in 0.18mim CMOS technology using Cadence Virtuoso. Achieving exceptional phase noise performance (-122.83 dBc/Hz at 1 MHz offset), it fulfills satellite communication requirements with reduced PFD dead zones, negligible current mismatch, and impressive dynamic range. Lock-in range: 8.69 GHz, capture range: 5 MHz, demonstrating the feasibility of a fully integrated PLL chip for superior satellite applications.

Autorentext

Dr. Shobha S. Nikam, with a BE, ME, and Ph.D. in Electronics & Telecommunication Engineering, is an Assistant Professor at AISSMS Institute of Information Technology, Pune. With 15 years of teaching, 1.5 years of research, and contributions to 18 international journals, 6 conferences, and an ISRO-UOP project.