USART Implementation using Verilog with Cypress-II

A universal synchronous asynchronous receiver / transmitter (USART) is a block of computer hardware that translates data between parallel and serial forms. The universal designation indicates that the data format and transmission speeds are configurable and that the actual electric signaling levels and typically is handled by a special driver circuit external to the USART. A USART is usually an individual (or part of an) integrated circuit used for serial communications over a computer or peripheral device serial port. In this book, the comprehensive research is put forward for an implementation on the basis of extensive reading and studying of associated papers and literature in this research area. The book caters to the needs of research fraternity and students in the field of VLSI and Embedded Systems design. The requirement for the readers of this book is to be familiar with the basics of Verilog, however R & D engineers from industry community working under Electronics group can also benefit from this book as a supplementary reference.

Autorentext

B. Siva Kumar Reddy est titulaire d'un B.Tech (E.C.E) et d'un M.Tech (conception de circuits intégrés à très grande échelle) de l'université technologique Jawaharlal Nehru, Hyderabad (JNTUH). Il prépare actuellement un doctorat dans le domaine du traitement des signaux pour les communications sans fil au National Institute of Technology, Warangal, Inde.