VHDL Answers to Frequently Asked Questions

VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complete simulatable examples. This book is intended for those who are seeking an enhanced proficiency in VHDL. Its target audience includes: 1. Engineers. The book addresses a set of problems commonly experienced by real users of VHDL. It provides practical explanations to the questions, and suggests practical solutions to the raised issues. It also includes packages to achieve common utilities, useful in the generation of debug code aDd testbench designs. These packages include conversions to strings (the IMAGE package), generation of Linear Feedback Shift Registers (LFSR), Multiple Input Shift Register (MISR), and random number generators.

Klappentext

emVHDL Answers to Frequently Asked Questions/em is a follow-up to the author's book emVHDL Coding Styles and Methodologies/em (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the emcomp.lang.vhdl/em newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error-free, and simulation-efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complex simulatable examples. This book is intended for those who are seeking an enhanced proficiency in VHDL. br/ This book differs from other VHDL books in many respects. This book:ul liemphasizes real VHDL, rather than philosophical or introductory types of information /li liemphasizes application of VHDL for synthesis /li liuses complete examples to demonstrate problems and solutions /li liprovides a disk that includes all the book examples and other useful reference VHDL material /li liuses easy to remember symbology notation to emphasize language rules, good and poor methodology and coding styles /li liidentifies obsolete VHDL constructs that must be avoided /li liidentifies synthesizable/non-synthesizable structures /li liuses a question and answer format to clarify and emphasize the concerns of VHDL users. /li /ul

Inhalt

1. Language Elements.- 2. Arrays.- 3. Drivers.- 4. Subprograms.- 5. Packages.- 6. Models.- 7. Synthesis.- 8. Design Verification and Testbench.- 9. Potpourri.- Appendix A: Vhdl'93 and Vhdl'87 Syntax Summary.- Appendix B: Package Standard.- Appendix C: Package Textio.- Appendix D: Package STDLogic1164.- Appendix E: Package STDLogicArith.- Appendix F: Vhdl Predefined Attributes.