VLSI Architecture for System on Chip (SOC) for Image Compression

The rapid growth of digital imaging applications, including desktop publishing, multimedia, teleconferencing, and high-definition television (HDTV) has increased the need for effective and standardized image compression techniques. This has become more popular with the help of System-On-Chip (SOC) technology, which gives low power, area, delay, cost requirements. Uncompressed multimedia (graphics, audio and video) data require considerable storage capacity and transmission bandwidth. The digitized video signal is compressed using DHT, DCT, DFT, DST and their combinations with DHT. Discrete Hartley Transform is used as basic transform because of its reversibility; hence other transform kernels can be developed from DHT. The architecture is developed using Verilog Hardware Descriptive Language and has been tested for still images. Simulation results show that the hybrid transform DHT+DCT achieves 81% compression ratio using the proposed architecture and its power, delay and area of the hybrid transform DHT+DCT has also been calculated. The work may be extended to derive a new single kernel transform which may have less complexity.

Autorentext

Dr. P. John Paul has 32 years of experience as an Academician, Researcher and Administrator including 5 years of Industrial experience in field of VLSI & Embedded Systems. Presently he is Principal of MRCE, Hyderabad. His contribution includes PhD supervision, Patent, 12 books, 24 Journals and 15 Conferences in the field of VLSI & Embedded Systems.