VLSI Architectures for Image Compression Applications

The field of ANN is moving forward in the domain of image processing especially for image compression and image enhancement. Software implementation of neural network architecture lacks the efficiency for commercial products, as they constrain the speed, increase area and predominantly the power. Hence there is always a need in developing mapping complex neural network architectures for image compression on hardware platforms. Hardware implementation of any complex architecture for commercial applications should be emphasized on reduction in power. Multi Layer Perceptron Neural Network structures have massive complex internal architectures, require more number of arithmetic units and consume large amount of power and area. Thus, power optimization techniques are needed to be designed. This can be possible either at architecture level or at algorithmic level or at physical level.The main objective of this research work is to design and optimize image compression algorithms using neural networks, and which should be compatible with hardware platforms for efficient implementation of these architectures with FPGA & ASIC.

Autorentext

Dr M. Lakshmi Kiran is working as an Associate Professor in the Department of ECE at SRIT (Autonomous), Anantapuramu. The author published 8 research papers in reputed international journals and conferences. Research interests: in VLSI, DIP and Communication Systems. Dr Kiran has 8 years of teaching experience & 4 years of research experience.