Wireless Network System in VLSI System Design

NoC built with reconfigurable routers allows the use of buffer switch smaller depths. These in turn have a similar performance with respect to NoC using a fixed size router, showing a large buffer depth and high-power dissipation. Analyses the reconfigurable router for low power and high performance with NoC architecture. Therefore the models are based on Network on a Chip (NoC) router is used to increase the reliability by avoiding errors and cross talk between the routers. By using swapping router can avoid deadlock conflicts and integrates dynamic arbiter to increase QoS (Quality of Service).The following objectives are Analysing the area, speed and power relation among them. Develop a utility that will go through all the implementation and come up with one having minimum power, efficient area and high speed. Research work is targeted mainly on implementing a simple and more adaptive VLSI architecture on NoC based system design.In enhance the security level on routing based methodology, the second part of the research work is on IBAAGKA (Identity-Based Authenticated Asymmetric Group Key Agreement) protocol for secured group communication by implementing FIFO ROUTING TECHNIQUE.

Autorentext

Dr.M Thamarai Selvan B.Sc., and M.Sc, in Electronics. He did Ph.D in VLSI System Design.He is currently working as an Assistant Professor, SRCAS, Coimbatore-06.Dr.N.Pasupathy, B.Sc., and M.Sc., in Physics, Trichy. He did Ph.D in Thin Flim from Bharathiar University. He is currently Working as an Associate Professor, Erode Arts and Science College.